This invention relates to semiconductor memory devices and more particularly to an improved MOS random access dynamic read/write memory having high speed pipe-line access.
One of the most widely used memory devices for computers is the MOS dynamic RAM of the type illustrated in U.S. Pat. No. 4,239,993 issued to McAlexander, White and Rao, assigned to Texas Instruments. As presently commercially available in the 64K-bit size, these devices have read access times of 150 nsec or less. Generally, a memory access time is selected to avoid wait conditions for the CPU. When higher speeds are needed, static RAM devices are used, having read access times of 55 nsec or below, but these are much more expensive, and consume more power.
In operation of a CPU, a statistical analysis shows that the main program memory is most often accessed with the next sequential address. Branches, interrupts, and the like present non-sequential addresses, but these occur in a minor percentage of the program fetches. Systems have been developed which are based on the theory that the next address is always accessed, and so processors are constructed which automatically fetch the next address; this data is available if needed, and is discarded if not.
It is the principal object of this invention to provide an improved high speed random access memory, particularly for a memory operating on a pre-fetch theory. Another object is to provide a semiconductor memory device which can implement high speed pipe-lined access with a minimum of off-chip circuitry. A further object is to provide an improved method of pipeline or sequential-address accessing of a memory device in a digital processor system.